MS Computer Science '22, BS Computer Science '21
University of California San Diego
Computer Architecture, Distributed Systems, Computer Security,
FPGA Security, Cryptography
(02/12/23): Turn on, Tune in, Listen up: Maximizing Channel Capacity in TDCs is a best paper candidate at ISFPGA1st,†,‡
(10/06/22): Recognized by Kastner Research Group for MS Research Award and my three years of work.
(09/26/22): After four years at UCSD, I have moved to Stanford to complete my PhD
(06/20/22): Received 2022 UCSD Department of Computer Science and Engineering MS Research Award
(05/18/22): Presented our open-source TDC implementation at the Workshop on Security for Custom Computing Machines1st,†,‡
(05/06/22): My master thesis "Next Generation Cloud-FPGA Side-Channels" was accepted by my Committee Chair, Prof. Ryan Kastner, and Committee Members, Prof. Dean Tullsen and Prof. Deian Stefan (UCSD)1st,‡
(02/11/22): Recognized by Kastner Research Group for DAC paper and presentation.
(12/05/21): Classifying Computations on Multi-Tenant FPGAs appeared as a paper at DAC2nd,†,‡
(09/01/21): Presented early stage Time-to-Digitial Converter research at the UC Santa Barbara Arch Lab1st,†,‡
(05/09/21): A Tunable Dual-Edge Time-to-Digital Converter appeared as an extended abstract at FCCM1st,†,‡
(02/28/21): Classifying Computations on Multi-Tenant FPGAs appeared as a poster at ISFPGA2nd
(1st, 2nd, 3rd,...) = my authorship role. (†) = I presented this work. (‡) = pdf available.
drewes at cs.stanford.edu